This invention relates generally to semiconductor logic gates, and more particularly, to logic gates employing field-effect transistors (FET's). In many applications of integrated circuitry, it is desirable to employ a basic logic circuit repeatedly, as a "building block" for more complex circuitry. Using a standard, repeatable logic circuit simplifies both design and fabrication.
The practicality of such an approach follows from well known theorems of Boolean algebra, in accordance with which practically any complex logical relationships among sets of digital signals can be reduced or transformed to a set of different relationships employing a single logic gate repeatedly.
For example, complex logic can be performed by interconnected combinations of a basic multi-input NOR gate. Logical functions, such as NOR, may be defined in various ways: either in terms of binary values, or true-or-false values, or different voltage levels. In terms of binary values, referred to as logic-1 and logic-0, respectively, the output of a NOR gate is a logic-1 output only if none of the inputs is a logic-1 value. If any one or more of the inputs is a logic-1, the logical OR of the inputs is also a logic-1, and the logical NOR of the inputs is a logic-0. It is possible to constrct much more complex logic using the NOR gate as the basic building block. It is equally possible to employ a NAND gate as the basic logic circuit, or a combination gate employing both OR and NAND functions.
Although theory allows the use of different gate structures as the basic logic gate, not all logic gates are equally advantageous in practice, and those that have been used or proposed prior to this invention have some significant drawbacks. A frequently used comparative measure for integrated circuits is the so-called speed-power product, which is more properly the propagation delay-power product. Ideally, both the propagation delay inherent in a circuit and the power dissipated in the circuit should be minimized. Hence the product of these two parameters, or the two considered separately, provide a good measure for comparing circuits that perform similar functions. As will be discussed in more detail, prior-art logic gate topologies are still in need of improvement in this respect.
Another important consideration in logic gate design is that the selected topology must permit expansion and interconnection of like logic gates in multiple stages. In general, this means that the ideal gate should accommodate multiple inputs and provide multiple outputs compatible with the inputs. Again, existing logic topologies do not meet this requirement in all respects.
It will be appreciated from the foregoing that there is still a significant need for a logic gate having a desirably low propagation delay-power product, and having the capability of being interconnected with like gates for purposes of forming more complex circuitry. As will next be described in summary form, the present invention satisfies this need.